In order to increase the speed of driving and reduce power consumption, a method for forming an integrated circuit by using an SOI (Silicon On Insulator) wafer provided with a thin single crystal Si layer on an insulating layer in place of a bulk (silicon) wafer has been developed. It is known that a parasitic capacitance can be decreased by forming an integrated circuit by using the SOI wafer. Usually, the SOI wafer is produced by a Smart Cut (registered trade mark) process using hydrogen ion implantation.
However, such a common SOI wafer uses a Si wafer having a diameter of 6 to 8 inches and, therefore, it is difficult to upsize a screen.
Then, in recent years, as disclosed in PTLs 1 to 6, methods for producing large-area SOI substrates have been disclosed, wherein the Smart Cut process and the like are used, a plurality of Si wafers are bonded side by side to a large glass substrate, and a Si film is transferred.
In this manner, an inexpensive large-area SOI substrate can be produced by bonding a plurality of Si wafers to a large glass substrate and transferring a Si film.
According to PTLs 1 and 2, Si wafers are placed side by side on a tray provided with a plurality of concave portions, hydrogen ions are implanted into the wafers to form fragile layers (damaged regions) and, thereafter, bonding to a glass substrate in a collective manner is performed. Subsequently, the glass substrate with Si wafers bonded is subjected to a heat treatment to induce separation at the fragile layers, so that the plurality of Si films are transferred to the glass substrate. In this manner, a SOI substrate in which the plurality of Si films have been transferred to the glass substrate can be obtained.
Here, in the case where a thin film transistor (TFT) or the like is formed, a Si film having a small film thickness is necessary. However, if a fragile layer is formed at somewhat shallow depth and the Si film having a small film thickness is transferred directly to a glass substrate, a hole is made in the Si film easily and the yield is decreased.
Consequently, a Si film having a film thickness larger than a predetermined film thickness is transferred to the glass substrate in advance. Then, the transferred Si film is irradiated with laser light to planarize the surface of the Si film. Thereafter, a so-called etch back treatment is applied to all over the surface of the glass substrate with the transferred Si film to decrease the thickness of the transferred Si film.
In the etch back treatment, the glass substrate with the transferred Si film having a film thickness larger than the predetermined film thickness is put into a chamber, a process gas is introduced into the chamber, and a dry etching treatment to generate plasma on the surface of the glass substrate is performed.
However, if a large glass substrate is subjected to the etch back treatment, the transferred Si film does not become thin uniformly.
FIG. 16 (a) is a plan view of a conventional semiconductor substrate before an etch back treatment. FIG. 16 (b) is a sectional view of FIG. 16 (a).
FIG. 17 (a) is a plan view of a conventional semiconductor substrate after an etch back treatment. FIG. 17 (b) is a sectional view of FIG. 17 (a).
As shown in FIGS. 16 (a) and (b), in a SOI substrate 800, transferred six Si wafers 810 are disposed non-contiguously on a large glass substrate 801. The Si wafer 810 is composed of a single crystal Si film 811 and a thermal oxidation film 812. The single crystal Si film 811 is disposed on the glass substrate 801 with the thermal oxidation film 812 therebetween. As an example, one Si wafer 810 has six panel-forming regions 850.
When the single crystal Si films 811 of this SOI substrate 800 are subjected to the etch back treatment, as shown in FIGS. 17 (a) and (b), the single crystal Si films 811 in corner portions and a central portion of the SOI substrate 800 are etched slowly under the influence of the in-plane distribution of an etching apparatus and thick film portions 803 having large film thicknesses are formed.
On the other hand, the single crystal Si films 811 located in the vertical and horizontal directions in the drawing shown in FIG. 17 (a) are etched quickly and, as shown in FIGS. 17 (a) and (b), thin film portions 804 having small film thicknesses are formed.
This is because the dry etching apparatus (parallel plate type RIE or ICP type RIE) of the large glass substrate has an etching rate distribution inherent in the apparatus.
In general, as for a dry etching apparatus of a large glass substrate, in the peripheral portion (in particular, corner portions), an electric field escapes easily, discharge density decreases easily, and the flow rate of an etching gas fed from a shower plate decreases easily, and in the central portion as well, the etching gas do not remain easily, so that in these regions, the etching rates are small.
Consequently, the etching rates have a doughnut type distribution, although it becomes difficult to improve the distribution in itself of these etching rates as the glass substrate becomes large.
In the case where the single crystal Si films 811 transferred to the large glass substrate 801 are subjected to the etch back treatment on the basis of dry etching by using these apparatuses, the single crystal Si films 811 become thick in the corner portion in which the etching rates are small and the single crystal Si films 811 become thin in the upper, lower, left, and right regions in which the etching rates are large.
As a result, the film thicknesses of the single crystal Si films 811 exhibit variations in the shape of a doughnut. In particular, as for the single crystal Si films 811 in the corner portion of the SOI substrate 800, the thick film portions 803 and the thin film portions 804 are formed in one Si film and, thereby, the film thickness variations occur in one Si film.
If TFTs (thin film transistors) are formed using the single crystal Si films 811 having film thickness variations as described above, the threshold voltages of TFTs fluctuate and, thereby, it becomes difficult to form TFT backplanes, which are required to have uniform TFT characteristics, for organic EL display devices and the like.
Meanwhile, the area of the single crystal Si films 811 having a uniform film thickness decreases by the etching treatment, so that the area of the panel-forming regions 850, in which the single crystal Si films 811 having a uniform film thickness are obtained, also decreases. Consequently, the panel layout efficiency decreases. As a result, a problem occurs in that the panel cost increases.
Such a problem in that the single crystal Si films 811 exhibit film thickness variations in the shape of a doughnut is a problem which peculiarly considerably occurs in the case where the SOI substrate with a plurality of Si films transferred to a large glass substrate is subjected to dry etching. This issue is not a serious problem in the case where a small substrate, e.g., a Si wafer or a SOI wafer serving as a small substrate, a small glass substrate, or a small SOI substrate, in which small glass substrates are bonded together in a one-to-one correspondence, is subjected to dry etching.
PTL 7 discloses a method in which the film thicknesses of a plurality of Si films, which have been bonded to a glass substrate and have been separated at the fragile layer, are decreased by CMP (chemical mechanical polishing).
In PTL 7, in consideration of variations in the amount of in-plane polishing by CMP, a plurality of types of Si wafers in which the depths of fragile layers formed in the Si wafers from the surface are different, are bonded to a glass substrate and, thereby, Si films having different film thicknesses are transferred. According to PTL 7, in a region in which the amount of polishing by CMP (chemical mechanical polishing) is large (for example, in the peripheral portion of the glass substrate), Si wafers with large depths of the fragile layers from the surfaces (that is, the Si film thickness after the transfer is large) are disposed on the glass substrate, and in a region in which the amount of polishing by CMP is small (for example, in the central portion of the glass substrate), Si wafers with small depths of the fragile layers from the surfaces (that is, the Si film thickness after the transfer is small) are disposed on the glass substrate.
Consequently, variations between film thicknesses of the plurality of Si films due to the difference in the amount of polishing treatment by CMP are prevented.
In PTL 7, as shown in FIG. 18 (a), a so-called bulk Si wafer 900 composed of a single crystal Si substrate 901 and a thermal oxidation film 902 disposed on the single crystal Si substrate 901 is used as a Si wafer before being bonded to the glass substrate.
Ions are implanted into the single crystal Si substrate 901 of the Si wafer 900 from the surface side of the thermal oxidation film 902, so as to form a fragile layer 903 in the single crystal Si substrate 901. In this case, the depth of the fragile layer 903 is adjusted in accordance with the amount of polishing by CMP thereafter. Then, a plurality of Si wafers 900 in which the fragile layer 903 is disposed in the single crystal Si substrate 901 are bonded to the large glass substrate 904. In this case, in a region in which the amount of polishing by CMP is large (for example, in the peripheral portion of the glass substrate), Si wafers with large depths of the fragile layers from the surfaces (that is, the Si film thickness after the transfer is large) are disposed on the glass substrate, and in a region in which the amount of polishing by CMP is small (for example, in the central portion of the glass substrate), Si wafers with small depths of the fragile layers from the surfaces (that is, the Si film thickness after the transfer is small) are disposed on the glass substrate.
Next, as shown in FIG. 18 (b), heat is applied and, thereby, a single crystal Si layer 905 which is part of the single crystal Si substrate 901 is separated along the fragile layer 903, and the remaining film is obtained as a Si film 906 transferred to the glass substrate 904. The surface of the resulting Si film 906 is polished by CMP, so that the film thickness of the Si film 906 is decreased.
In PTL 8, a SOI wafer, in which a BOX (buried oxide) layer made from SiO2 is disposed in the inside of the single crystal Si layer, is used and the SOI wafer provided with the fragile layer in the BOX layer rather than in a single crystal Si substrate is transferred to the glass substrate.
According to PTL 8, as shown in FIG. 19 (a), ions are implanted into the SOI wafer 910, in which a Si support substrate 911, the BOX layer 912, a SOI layer 913 formed from single crystal Si, and a thermal oxidation film 914 are stacked sequentially from the surface side of the thermal oxidation film 914, so that a fragile layer 915 is formed in the BOX layer 912.
Subsequently, as shown in FIG. 19 (b), the SOI wafer 910 provided with the fragile layer 915 in the BOX layer 912 is bonded to the glass substrate 904.
Then, the SOI wafer 910 bonded to the glass substrate 904 is separated at the fragile layer 915 in the BOX layer 912 by applying heat, and the thermal oxidation film 914, the SOI layer 913, and part of the BOX layer 912 are transferred to the glass substrate 904. Thereafter, the BOX layer 912 transferred to the glass substrate 904 is removed by wet etching. Consequently, the SOI layer 913 disposed between the BOX layer 912 removed and the thermal oxidation film 914 is exposed and the plurality of SOI layers 913 having a uniform film thickness can be transferred to the glass substrate 904.
According to the method of PTL 8, crystal defects formed in the layer because of formation of the fragile layer 915 are limited in the BOX layer 912 and are not formed in the SOI layer 913. Meanwhile, the BOX layer 912 remaining after separation at the fragile layer 915 is removed by wet etching and, thereby, the SOI layer 913 between the BOX layer 912 and the thermal oxidation film 914 is exposed, so that the SOI layer 913 having a uniform film thickness can be obtained.